1. Field of the Invention
This invention relates generally to programmable semiconductor memories, and more particularly, to the configuration of a memory device incorporating flash memory cells.
2. Cross-Reference to Related Case
This case is related to FLASH MEMORY ARRAY ARCHITECTURE AND METHOD OF PROGRAMMING, ERASING, AND READING THEREOF, invented by Sameer Haddad, filed Dec. 11, 2001, Ser. No. 10/013,993.
3. Discussion of the Related Art
A type of programmable memory cell is commonly referred to as a flash memory cell. Such flash memory cell may include a source and a drain formed in a silicon substrate, or in a well that is formed in the silicon substrate. The flash memory cell includes a stacked gate structure formed on the silicon substrate. The region of the silicon substrate beneath the stacked gate structure is known as the channel region of the flash memory cell.
The stacked gate structure of the flash memory cell includes a pair of polysilicon structures separated by oxide layers. One of the polysilicon structures functions as a floating gate and the other polysilicon structure functions as a control gate for the flash memory cell. The oxide layer that separates the floating gate from the silicon substrate is commonly referred to as a tunnel oxide layer. A memory cell of this type is shown and described in U.S. Pat. No. 4,698,787, xe2x80x9cSingle Transistor Electrically Programmable Memory Device and Methodxe2x80x9d, issued to Mukheree et al. on Oct. 6, 1987.
Programming operations on a flash memory cell involve the application of a relatively large constant voltage to the drain of the flash memory cell wile an even larger voltage is applied to the control gate. During such a programming operation, the source of the flash memory cell is maintained at a ground level or a zero voltage level in relation to the voltages applied to the control gate and drain. The high constant voltage applied to the control gate raises the voltage potential of the floating gate to a high level at the start of the programming operation. Such a high voltage potential on the floating gate attracts the electrons floating through the channel region. Under these conditions, electrons in the channel region having sufficiently high kinetic energy migrate through the tunnel oxide layer and onto the floating gate. This phenomenon is commonly referred to as hot carrier programming or hot carrier injection. A successful programming operation involves the injection of sufficient numbers of electrons onto the floating gate to achieve a desired threshold voltage for the flash memory cell. The threshold voltage is the voltage that must be applied to the control gate of the flash memory cell to cause conduction through the channel region during the read operation on the flash memory cell.
FIG. 1 illustrates what is known as a NOR memory array 100. The array includes individual cells C1-C16 made up of respective MOS field effect transistors T1-T16, each of the transistors including a source S, a drain D, a floating gate FG, and a control gate CG as described above, bit lines B0-B3, and word lines W0-W3. The cells are connected in an array of rows 102, 104, 106, 108 and columns 110, 112, 114, 116, with the control gates of the cells in a row (for example row 104) being connected to a respective word line (W1) and the drains of the cells in a column (for example column 114) being connected to a respective bit line (B2). The sources of the cells in a column are connected together. It will be understood that FIG. 1 shows only a small portion of the array, which portion is repeated to form the entire array.
A cell can be programmed by applying programming voltages of approximately 9-10 volts to the control gate, approximately 5 volts to the drain, and grounding the source. These voltages cause hot electrons to be injected from a drain depletion region into the floating gate. Upon removal of the programming voltages, the injected electrons are trapped in the floating gate and create a negative charge therein that increases the threshold of the cell to a value in excess of approximately 4 volts.
A cell can be read by applying a voltage of approximately 5 volts to the control gate, applying approximately 1 volt to the bit line to which the drain is connected, grounding the source, and sensing the bit line current. If the cell is programmed and the threshold voltage is relatively high (4 volts), the bit line current will be zero or relatively low. If the cell is not programmed or is erased, the threshold voltage will be relatively low (2 volts), the control gate voltage will enhance the channel, and the bit line current will be relatively high.
A cell can be erased in several ways. In one approach, applying a relatively high voltage, typically 12 volts, to the source, grounding the control gate and allowing the drain to float erases a cell. This causes the electrons that were injected into the floating gate during programming to undergo Fowler-Nordheim tunneling from the floating gate through the thin tunnel oxide layer to the source. Applying a negative voltage on the order of xe2x88x9210 volts to the control gate, applying 5 volts to the source and allowing the drain to float can also erase the cell. Another method of erasing a cell is by applying 5 volts to the P well and xe2x88x9210 volts to the control gate while allowing the source and drain to float.
The array of FIG. 1 is shown in layout form in FIG. 2. The layout structure includes elongated, substantially parallel source/drain regions 120, 122, 124, 126, each made up of alternating sources S and drains D, a channel region CR connecting each adjacent source and drain as shown. Each bitline B0-B3 is associated with a respective source/drain region 120, 122, 124, 126, running therealong and contacting the individual drains of its associated source/drain region by means of contacts 130. The word lines of the structure are shown at W0-W3, and are orthogonal to the bit lines B0-B3. The sources S of the source/drain regions 120, 122, 124, 126 are connected together in a direction parallel to the word lines W0-W3 as shown in FIG. 2, being formed by a self-aligned-source (SAS) process as for example disclosed in U.S. Pat. No. 5,120,671, xe2x80x9cProcess For Self Aligning A Source Region With A Field Oxide Region And A Polysilicon Gatexe2x80x9d, issued to Tangetal. on Jun. 9, 1992. Cells C1-C16 are formed at the intersections of word lines W0-W3 and bit lines B0-B3. Approximately every 20 bit lines across the array 100, each self aligned source SAS is brought into contact with conductive lines CL running substantially parallel to the bit lines B0-B3 by means of contacts 132. The conductive lines CL are connected together by a connecting line 134 to which appropriate voltage Vss may be applied so that a common voltage may be applied to all the sources S.
The NOR architecture provides several advantages. With the ability to access each cell individually, a high level of drive current can be achieved so that the read speed is high. Furthermore, this architecture lends itself to reasonable device scaling, i.e., minimizing of the feature sizes, i.e., for example, minimizing of dimensions of active regions, isolation regions, word and bit lines.
However, such an architecture is subject to problems. For example, as described in U.S. Pat. No. 5,656,513, xe2x80x9cNonvolatile Memory Cell Formed Using Self-Aligned Source Implantxe2x80x9d issued to Wang et al., issued Aug. 12, 1997 (assigned to the present Assignee), in the self-aligned-source process, a selective etch is undertaken to etch away tunnel oxide and field oxide between the word lines, this etch aligning with the edges of the word lines. While this etch is selective in that it etches the oxide at a much higher rate than the polysilicon word lines or silicon, it is not totally selective. Portions of the silicon of the source, as well as portions of the exposed polysilicon of the word lines, are etched away. The etch operates on tunnel oxide at the same rate as field oxide. Field oxide is typically considerably thicker than tunnel oxide. By the time the inter source portions of field oxide are removed, not only has the etch removed the gate oxide overlying the source, but it has also removed a portion of the silicon substrate in the source, producing a gouge therein, which can significantly affect device performance. Furthermore, the process itself is relatively complicated, requiring implantation in the exposed silicon to provide proper connection of cell sources, along with achieving low resistance.
Furthermore, the conductive lines CL, which contact the self aligned sources SAS, being spaced for example every 20 bit lines apart across the array, use up valuable space in the layout, which works against further miniaturization of the overall array.
Another problem is that of column leakage. Because of manufacturing tolerances, during the erase process, some cells become overerased before other cells become sufficiently erased. The floating gates of the overerased cells are either completely or partially depleted of electrons and have a very low negative charge or become positively charged. The overerased cells can function as depletion mode transistors that cannot be turned off by normal operating voltages applied to their control gates and introduce leakage current to the bit line during subsequent program and read operations. The slightly overerased cells can introduce varying amounts of leakage current to the bit line depending upon the extent of overerasure.
More specifically, during program and read operations only one word line is held high at a time, while the other word lines are grounded. However, because a positive voltage is applied to the drains of all the cells, if the threshold voltage of an unselected cell is very low, zero or negative, a leakage current will flow through the source, channel and drain of that cell.
Additionally, it is desirable to decrease the size of conventional memory cells in order to increase their density in the memory array. This may be accomplished by decreasing the dimensions of the floating gates and therefore the dimensions of the gate stack. However, as the dimensions of the gate stack decrease, the length of the channel regions decreases. As the source and drain of a conventional cell become closer, short channel effects may cause the threshold voltage of the cell to drop below a desired level, leading to undesirable leakage of current through the cell.
FIG. 3 illustrates what is known as a NAND memory array 200. The array again includes individual cells C1-C16 made up of respective MOS field effect transistors T1-T16, each of the transistors T1-T16 including a source S, a drain D, a floating gate FG, and a control gate CG as described above. The array 200 is made up of a plurality of memory cell columns or strings 202, 204, 206, 208, each of which has a number of memory cell transistors (column 202, T1, T5 . . . ), for example, 16 such transistors, connected in series. Each string is connected through a select gate SG1 at one end thereof to a bit line B0-B3, and, through another select gate SG2 at the other end thereof to a source line SL0-SL3. The control gates CG of the cells in a row 210, 212, 214, 216 are connected to a respective word line W0-W3. Again, it will be understood that FIG. 3 shows only a small portion of the array, which portion is repeated to form the entire array.
The individual cells are programmed and erased by applying voltages to the source, drain and control gate thereof as described above. In reading the state of an individual (xe2x80x9cselectedxe2x80x9d) cell in a string, the select gates of that string are turned on, and the control gates of each of the cells in that string other than the selected cell, i.e., the xe2x80x9cunselectedxe2x80x9d cells, are driven sufficiently high to turn on each of those transistors, whether they are programmed or not. Then, a lower level of voltage is applied to the control gate of the selected cell, which level would be sufficient to turn on the transistor of that cell if the cell were unprogrammed, but insufficient to turn on that cell if the transistor of that cell were programmed. Data stored in the selected cell is then read out depending on whether the selected cell is turned on or off, i.e., whether current flows or does not flow through the memory cell string.
Since the transistors in each string are connected in series, this array does not require the self-aligned-source process as used in the NOR array configuration. However, because all of the non-selected transistors in a strings are rendered conductive in the process of reading the state of a selected cell, the drive current for reading an individual cell is lower than in the NOR array, resulting in cell read speed being substantially slower than in the NOR array configuration.
What is needed is a memory array wherein high access speed to individual cells is achieved, wherein the problems associated with the self aligned source process are avoided, wherein column leakage and short channel effect are reduced, and which readily lends itself to scaling.
The present memory array includes a plurality of bit lines and a plurality of word lines orthogonal to the bit lines. The array includes a plurality of sets of transistors, each set including a pair of transistors in series, each pair connected between a pair of adjacent bit lines, with each one of the pair being associated with a different word line. In the layout of the array, a plurality of source/drain regions of substantially straight configuration are included, each comprising alternating source and drain regions along its length. Each bitline, zigzag in configuration, is connected to two source/drain regions in alternate manner along the bitline length.